000 02176 a2200217 4500
005 20250829161323.0
020 _a0792383214
020 _a9780792383215
082 0 4 _a621.395
_bNAT
100 1 _aMaheshwari, Naresh
_9100958
245 1 0 _aTiming analysis and optimization of sequential circuits
_cNaresh Maheshwari
260 _aNew Delhi:
_bSpringer,
_c1998.
300 _axv, 208p.
500 _aHB
520 _aRecent years have seen rapid strides in the level of sophistication of VLSI circuits. On the performance front, there is a vital need for techniques to design fast, low-power chips with minimum area for increasingly complex systems, while on the economic side there is the vastly increased pressure of time-to-market. These pressures have made the use of CAD tools mandatory in designing complex systems. Timing Analysis and Optimization of Sequential Circuits describes CAD algorithms for analyzing and optimizing the timing behavior of sequential circuits with special reference to performance parameters such as power and area. A unified approach to performance analysis and optimization of sequential circuits is presented. The state of the art in timing analysis and optimization techniques is described for circuits using edge-triggered or level-sensitive memory elements. Specific emphasis is placed on two methods that are true sequential timing optimizations techniques: retiming and clock skew optimization. Timing Analysis and Optimization of Sequential Circuits covers the following topics: - Algorithms for sequential timing analysis - Fast algorithms for clock skew optimization and their applications - Efficient techniques for retiming large sequential circuits - Coupling sequential and combinational optimizations. Timing Analysis and Optimization of Sequential Circuits is written for graduate students, researchers and professionals in the area of CAD for VLSI and VLSI circuit design.
546 _aEng
650 4 _aComputer-aided design
_9100959
650 4 _aIntegrated circuits-Very larges cale Integration-Design and construction-data processing
_9100960
650 4 _aTime-series analysis-data processing
_9100961
942 _cBK
999 _c37845
_d37845