MARC details
| 000 -LEADER |
|---|
| fixed length control field |
02868 a2200409 4500 |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
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| control field |
20250829160507.0 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
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| International Standard Book Number |
0387465464 |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER |
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| Classification number |
621 |
| Item number |
SAD |
| 100 1# - MAIN ENTRY--PERSONAL NAME |
|---|
| Personal name |
Sachdev, Manoj |
| 9 (RLIN) |
73355 |
| 245 10 - TITLE STATEMENT |
|---|
| Title |
Defect-oriented testing for nano-metric cmos vlsi circuits |
| Statement of responsibility, etc. |
Manoj Sachdev. |
| 250 ## - EDITION STATEMENT |
|---|
| Edition statement |
2nd ed. |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. |
|---|
| Place of publication, distribution, etc. |
Dordrecht : |
| Name of publisher, distributor, etc. |
Springer, |
| Date of publication, distribution, etc. |
2007. |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
xxi, 328p. |
| 500 ## - GENERAL NOTE |
|---|
| General note |
HB |
| 520 ## - SUMMARY, ETC. |
|---|
| Summary, etc. |
Failures of nano-metric technologies owing to defects and shrinking process tolerances give rise to significant challenges for IC testing. As the variation of fundamental parameters such as channel length, threshold voltage, thin oxide thickness and interconnect dimensions goes well beyond acceptable limits, new test methodologies and a deeper insight into the physics of defect-fault mappings are needed. In Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits state of the art of defect-oriented testing is presented from both a theoretical approach as well as from a practical point of view. Step-by-step handling of defect modeling, defect-oriented testing, yield modeling and its usage in common economics practices enables deeper understanding of concepts. The progression developed in this book is essential to understand new test methodologies, algorithms and industrial practices. Without the insight into the physics of nano-metric technologies, it would be hard to develop system-level test strategies that yield a high IC fault coverage. Obviously, the work on defect-oriented testing presented in the book is not final, and it is an evolving field with interesting challenges imposed by the ever-changing nature of nano-metric technologies. Test and design practitioners from academia and industry will find that Defect-Oriented Testing for Nano-Metric CMOS VLSI Circuits lays the foundations for further pioneering work. |
| 546 ## - LANGUAGE NOTE |
|---|
| Language note |
Eng |
| 650 #4 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Circuits & components. |
| 9 (RLIN) |
2635 |
| 650 #4 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Mathematics and Science. |
| 9 (RLIN) |
61627 |
| 650 #4 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Technology & Engineering. |
| 9 (RLIN) |
73356 |
| 650 #4 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Technology & Industrial Arts. |
| 9 (RLIN) |
96 |
| 650 #4 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Science/Mathematics. |
| 9 (RLIN) |
73357 |
| 650 #4 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Electricity. |
| 9 (RLIN) |
73358 |
| 650 #4 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Electronics - Circuits - General. |
| 9 (RLIN) |
73359 |
| 650 #4 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Engineering - Electrical & Electronic. |
| 9 (RLIN) |
458 |
| 650 #4 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Industrial Design - General. |
| 9 (RLIN) |
73360 |
| 650 #4 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Technology / Electronics / Circuits / General. |
| 9 (RLIN) |
73361 |
| 650 #4 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Technology / Electronics / Microelectronics. |
| 9 (RLIN) |
73362 |
| 650 #4 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Technology / Engineering / Electrical. |
| 9 (RLIN) |
73363 |
| 650 #4 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Technology / Industrial Design / General. |
| 9 (RLIN) |
73364 |
| 650 #4 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Defects. |
| 9 (RLIN) |
73365 |
| 650 #4 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Integrated circuits. |
| 9 (RLIN) |
73366 |
| 650 #4 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Metal oxide semiconductors, Complementary. |
| 9 (RLIN) |
73367 |
| 650 #4 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Testing. |
| 9 (RLIN) |
73368 |
| 650 #4 - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name entry element |
Very large scale integration. |
| 9 (RLIN) |
73369 |
| 700 1# - ADDED ENTRY--PERSONAL NAME |
|---|
| Personal name |
Gyvez, Jose pineda (jt. auth.) |
| 9 (RLIN) |
73370 |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
|---|
| Koha item type |
Books |
