Timing analysis and optimization of sequential circuits (Record no. 37845)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 02176 a2200217 4500 |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20250829161323.0 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 0792383214 |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 9780792383215 |
| 082 04 - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 621.395 |
| Item number | NAT |
| 100 1# - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Maheshwari, Naresh |
| 9 (RLIN) | 100958 |
| 245 10 - TITLE STATEMENT | |
| Title | Timing analysis and optimization of sequential circuits |
| Statement of responsibility, etc. | Naresh Maheshwari |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. | |
| Place of publication, distribution, etc. | New Delhi: |
| Name of publisher, distributor, etc. | Springer, |
| Date of publication, distribution, etc. | 1998. |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | xv, 208p. |
| 500 ## - GENERAL NOTE | |
| General note | HB |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc. | Recent years have seen rapid strides in the level of sophistication of VLSI circuits. On the performance front, there is a vital need for techniques to design fast, low-power chips with minimum area for increasingly complex systems, while on the economic side there is the vastly increased pressure of time-to-market. These pressures have made the use of CAD tools mandatory in designing complex systems. Timing Analysis and Optimization of Sequential Circuits describes CAD algorithms for analyzing and optimizing the timing behavior of sequential circuits with special reference to performance parameters such as power and area. A unified approach to performance analysis and optimization of sequential circuits is presented. The state of the art in timing analysis and optimization techniques is described for circuits using edge-triggered or level-sensitive memory elements. Specific emphasis is placed on two methods that are true sequential timing optimizations techniques: retiming and clock skew optimization. Timing Analysis and Optimization of Sequential Circuits covers the following topics: - Algorithms for sequential timing analysis - Fast algorithms for clock skew optimization and their applications - Efficient techniques for retiming large sequential circuits - Coupling sequential and combinational optimizations. Timing Analysis and Optimization of Sequential Circuits is written for graduate students, researchers and professionals in the area of CAD for VLSI and VLSI circuit design. |
| 546 ## - LANGUAGE NOTE | |
| Language note | Eng |
| 650 #4 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Computer-aided design |
| 9 (RLIN) | 100959 |
| 650 #4 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Integrated circuits-Very larges cale Integration-Design and construction-data processing |
| 9 (RLIN) | 100960 |
| 650 #4 - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Time-series analysis-data processing |
| 9 (RLIN) | 100961 |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | Books |
| Withdrawn status | Lost status | Damaged status | Not for loan | Home library | Current library | Shelving location | Date acquired | Total checkouts | Full call number | Barcode | Date last seen | Price effective from | Koha item type |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Central Library Allama Iqbal Open University Islamabad | Central Library Allama Iqbal Open University Islamabad | General Stacks | 10/04/2008 | 621.395 NAT | 110120 | 10/02/2017 | 10/02/2017 | Books |